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The latest badge promoting the Intel Core branding. The following is a list of Intel Core processors.This includes Intel's original Core (Solo/Duo) mobile series based on the Enhanced Pentium M microarchitecture, as well as its Core 2- (Solo/Duo/Quad/Extreme), Core i3-, Core i5-, Core i7-, Core i9-, Core M- (m3/m5/m7/m9), Core 3-, Core 5-, and Core 7- Core 9-, branded processors.
An iterative refresh of Raptor Lake-S desktop processors, called the 14th generation of Intel Core, was launched on October 17, 2023. [1] [2]CPUs in bold below feature ECC memory support only when paired with a motherboard based on the W680 chipset according to each respective Intel Ark product page.
All models support: SSE4.1, SSE4.2, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, AES-NI, Smart Cache, DL Boost, GNA 3.0, and Optane memory. All models support up to DDR5-4800 or DDR4-3200 memory, and 16 lanes of PCI Express 5.0 + 4 lanes of PCIe 4.0.
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Enhanced Intel SpeedStep Technology (EIST), Intel Turbo Boost, Intel 64, XD bit (an NX bit implementation), Intel VT-x, AES-NI, ECC memory. All models except C2x38 support Intel QuickAssist Technology (cryptography accelerator)
List of AMD Athlon 64 processors; List of AMD Athlon XP processors; ... Saturn Nibble CPU (4-bit) Hitachi ... List of Intel Core processors.
The following is a partial list of Intel CPU microarchitectures. The list is incomplete, additional details can be found in Intel's tick–tock model, process–architecture–optimization model and Template:Intel processor roadmap.
All models support uni-processor configurations only. Intel HD Graphics P4000 uses drivers that are optimized and certified for professional applications, similar to nVidia Quadro and AMD FirePro products.
Itanium 2 uses socket PAC611 with a 128 bit wide FSB.The 90 nm CPUs (9000 and 9100 series) bring dual-core chips and an updated microarchitecture adding multithreading and splitting the L2 cache into a 256 KB data cache and 1 MB instruction cache per core (the pre-9000 series L2 cache being a 256 KB common cache).
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