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  2. Open collector - Wikipedia

    en.wikipedia.org/wiki/Open_collector

    For an NPN open emitter output, the collector is connected to the positive voltage rail, so the emitter outputs a high voltage when the transistor is on and is hi-Z when off. For a PNP open emitter output, the collector is connected to the low voltage supply, so the emitter outputs a low voltage when the transistor is on and is hi-Z when off.

  3. Integrated injection logic - Wikipedia

    en.wikipedia.org/wiki/Integrated_injection_logic

    The heart of an I2L circuit is the common emitter open collector inverter. Typically, an inverter consists of an NPN transistor with the emitter connected to ground and the base biased with a forward current from the current source. The input is supplied to the base as either a current sink (low logic level) or as a high-z floating condition ...

  4. Common collector - Wikipedia

    en.wikipedia.org/wiki/Common_collector

    The transistor continuously monitors V diff and adjusts its emitter voltage to equal V in minus the mostly constant V BE (approximately one diode forward voltage drop) by passing the collector current through the emitter resistor R E. As a result, the output voltage follows the input voltage variations from V BE up to V +; hence the name ...

  5. Current-mode logic - Wikipedia

    en.wikipedia.org/wiki/Current-mode_logic

    Current mode logic (CML), or source-coupled logic (SCL), is a digital design style used both for logic gates and for board-level digital signaling of digital data.. The basic principle of CML is that current from a constant current generator is steered between two alternate paths depending on whether a logic zero or logic one is being represented.

  6. Wired logic connection - Wikipedia

    en.wikipedia.org/wiki/Wired_logic_connection

    Open-emitter buffers connected as wired OR. See also: Diode logic § Active-high OR logic gate. The wired OR connection electrically performs the Boolean logic operation of an OR gate using open emitter or similar inputs (which can be identified by the ⎏ symbol in schematics) connected to a shared output with a pull-down resistor. This gate ...

  7. Direct-coupled transistor logic - Wikipedia

    en.wikipedia.org/wiki/Direct-coupled_transistor...

    If the V CE(SAT ) is too low, the next gate will not open up. [6] If you want only a certain amount of circuits open, then the V CE(SAT) needs to be smaller than the next transistor V BE(ON) (voltage input) between the base and emitter. It depends on your desired function. [6] Series gating is a little different.

  8. The best matching lounge sweats to scoop up at Amazon ... - AOL

    www.aol.com/the-best-matching-lounge-sweats-to...

    This V-neck number's ribbed knit top and high-waisted pants complete its casual-chic, vaguely retro vibe, and you'll be psyched to combine the pieces with other chillax-time all-stars in your ...

  9. List of network buses - Wikipedia

    en.wikipedia.org/wiki/List_of_network_buses

    Open collector. Single conductor, with 5 V power supply and ground, shielded when using higher speeds sync. and async. transmission, variable up to ~150 kbit/s