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Dual processor Nehalem-based Xeon chipsets [ edit ] The Nehalem-based Xeons for dual-socket systems, initially launched as the Xeon 55xx series, feature a very different system structure: the memory controllers are on the CPU, and the CPUs can communicate with one another as peers without going via the chipset.
Xeon D-1513N: SR3KV (A1) 4 1.6 GHz 2.2 GHz 4 × 256 KB: 6 MB: 35 W ... Xeon E5-26xx v4 (dual-processor) Model number sSpec number Cores Frequency Turbo L2 cache L3
Xeon Silver (dual processor) Model number sSpec number Cores (threads) Frequency Turbo Boost all-core/2.0 (/max. 3.0) L2 cache L3 cache TDP Socket I/O bus Memory
Based on NetBurst microarchitecture; All models support: MMX, SSE, SSE2, Hyper-Threading All models support dual-processor configurations; Models with no suffix or the A suffix use Socket 603 and a 400 MT/s FSB while models with the B suffix use Socket 604 and a 533 MT/s FSB.
Xeon Platinum supports up to eight sockets; Xeon Gold supports up to four sockets; Xeon Silver and Bronze support up to two sockets; No suffix letter: up to 1.0TB DDR4 per socket-L: Large DDR memory tier support (up to 4.5TB)-M: Medium DDR memory tier support (up to 2.0TB)-N: Network & NFV specialized-R: Refresh (higher performance)
Official designation now Xeon; i.e. not "Pentium 4 Xeon" Xeon 1.4, 1.5, 1.7 GHz Introduced May 21, 2001; L2 cache was 256 KB Advanced Transfer cache (integrated) Processor package Organic Land Grid Array 603 (OLGA 603) System bus clock rate 400 MHz; SSE2 SIMD Extensions; Used in high-performance and mid-range dual processor enabled workstations
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