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2. PCI Express - Wikipedia

   en.wikipedia.org/wiki/PCI_Express

   PCI Express Mini Card (also known as Mini PCI Express, Mini PCIe, Mini PCI-E, mPCIe, and PEM), based on PCI Express, is a replacement for the Mini PCI form factor. It is developed by the PCI-SIG . The host device supports both PCI Express and USB 2.0 connectivity, and each card may use either standard.

3. List of AMD chipsets - Wikipedia

   en.wikipedia.org/wiki/List_of_AMD_chipsets

   OR single PCI-E 2.0 x16 Mobile Chipset, Tigris platform AMD 880M chipset Athlon II Neo, Turion II Neo Radeon HD 4225 No DirectX 10.1, UVD2, HDMI/HDCP, DisplayPort, DVI, VGA, OR Single PCI-E 2.0 x16 Mobile Chipset, Nile platform AMD 880M chipset Mobile Phenom II, Mobile Turion II, Mobile Athlon II, Mobile Sempron V-Series Radeon HD 4250 Radeon ...

4. List of Intel Xeon chipsets - Wikipedia

   en.wikipedia.org/wiki/List_of_Intel_Xeon_chipsets

   PCI Express 1 ×16 or 2 ×8 ports, single 32-bit 33 MHz PCI bus, DMI for ICH7 3200: Bigby-V 800 or 1066 or 1333 MT/s Two channels of ECC DDR2-667 or DDR2-800 PCI Express ×8 port, single 32-bit 33 MHz PCI bus, DMI for ICH9 ICH9 3210: Bigby-P PCI Express 1 ×16 or 2 ×8 ports, single 32-bit 33 MHz PCI bus, DMI for ICH9

5. Direct Media Interface - Wikipedia

   en.wikipedia.org/wiki/Direct_Media_Interface

   DMI is essentially PCI Express, using multiple lanes and differential signaling to form a point-to-point link. Most implementations use a ×8 or ×4 link, while some mobile systems (e.g. 915GMS, 945GMS/GSE/GU and the Atom N450) use a ×2 link, halving the bandwidth. The original implementation provides 10 Gbit/s (1 GB/s) in each direction using ...

6. PCI configuration space - Wikipedia

   en.wikipedia.org/wiki/PCI_configuration_space

   One of the major improvements the PCI Local Bus had over other I/O architectures was its configuration mechanism. In addition to the normal memory-mapped and I/O port spaces, each device function on the bus has a configuration space, which is 256 bytes long, addressable by knowing the eight-bit PCI bus, five-bit device, and three-bit function numbers for the device (commonly referred to as the ...

7. 16-pin 12VHPWR connector - Wikipedia

   en.wikipedia.org/wiki/16-Pin_12vHPWR_connector

   PCI-SIG, the standards organization responsible for the creation of the 12VHPWR connector, has decided to make changes to the connector's specifications following the failures. [ 14 ] A class-action lawsuit has been filed against Nvidia over melting 12VHPWR cables which the lawsuit states is "a dangerous product that should not have been sold ...

8. nForce4 - Wikipedia

   en.wikipedia.org/wiki/NForce4

   Support for up to 20 PCI Express (PCIe) lanes (up to 38-40 lanes for the nForce4 SLI x16). Reference boards are set up with one x16 slot and three x1 slots, leaving 1 lane unused. Support for up to 10 USB 2.0 ports. Support for 4 SATA and 4 PATA drives, which can be linked together in any combination of SATA and PATA to form a RAID 0, 1, or 0+1.

9. Mobile PCI Express Module - Wikipedia

   en.wikipedia.org/wiki/Mobile_PCI_Express_Module

   Mobile PCI Express Module (MXM) is an interconnect standard for GPUs (MXM Graphics Modules) in laptops using PCI Express created by MXM-SIG. The goal was to create a non-proprietary, industry standard socket, so one could easily upgrade the graphics processor in a laptop, without having to buy a whole new system or relying on proprietary vendor upgrades.