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The original Verilog simulator, Gateway Design's Verilog-XL was the first (and only, for a time) Verilog simulator to be qualified for ASIC (validation) sign-off. After its acquisition by Cadence Design Systems, Verilog-XL changed very little over the years, retaining an interpreted language engine, and freezing language-support at Verilog-1995.
Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95. In the same time frame Cadence initiated the creation of Verilog-A to put standards support behind its analog simulator Spectre. Verilog-A was never intended to be a standalone language and is a subset of Verilog-AMS which encompassed ...
MyHDL [1] is a Python-based hardware description language (HDL).. Features of MyHDL include: The ability to generate VHDL and Verilog code from a MyHDL design. [2]The ability to generate a testbench (Conversion of test benches [3]) with test vectors in VHDL or Verilog, based on complex computations in Python.
The Verilog Procedural Interface (VPI), originally known as PLI 2.0, is an interface primarily intended for the C programming language.It allows behavioral Verilog code to invoke C functions, and C functions to invoke standard Verilog system tasks.
Here the design is mapped into a hardware accelerator to run much faster and the testbench (and any behavioral design code) continues to run on the simulator on the workstation. A high-bandwidth, low latency channel connects the workstation to the accelerator to exchange signal data between testbench and design.
An HDL simulator — the program that executes the testbench — maintains the simulator clock, which is the master reference for all events in the testbench simulation. Events occur only at the instants dictated by the testbench HDL (such as a reset-toggle coded into the testbench), or in reaction (by the model) to stimulus and triggering events.
To simulate an e-testbench with a design written in VHDL/Verilog, Specman must be run in conjunction with a separate HDL simulation tool. Specman is a feature of Cadence's new Xcelium simulator, where tighter product integration offers both faster runtime performance and debugs capabilities not available with other HDL simulators.
In semulation one part of a hardware design is processed sequential in software (e.g. the testbench) while the other part is emulated. An example design flow for semulation is depicted in the following block chart: The database holds the design and testbench files and the information about the block whether it will be simulated or emulated.