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Some ECC-enabled boards and processors are able to support unbuffered (unregistered) ECC, but will also work with non-ECC memory; system firmware enables ECC functionality if ECC memory is installed. ECC may lower memory performance by around 2–3 percent on some systems, depending on the application and implementation, due to the additional ...
The chipsets contain a 'memory controller hub' and an 'I/O controller hub', which tend to be called 'north bridge' and 'south bridge' respectively. The memory controller hub connects to the processors, memory, high-speed I/O such as PCI Express, and to the I/O controller hub by a proprietary link.
Hence, an ECC memory can support the scrubbing of the memory content. Namely, if the memory controller scans systematically through the memory, the single bit errors can be detected, the erroneous bit can be determined using the ECC checksum , and the corrected data can be written back to the memory.
One example is the Linux kernel's EDAC subsystem (previously known as Bluesmoke), which collects the data from error-checking-enabled components inside a computer system; besides collecting and reporting back the events related to ECC memory, it also supports other checksumming errors, including those detected on the PCI bus.
DDR3L/LPDDR3/LPDDR4 dual-channel memory controller supporting up to 8 GB; support for DDR3L with ECC; Display controller with 1 MIPI DSI port and 2 DDI ports (eDP 1.3, DP 1.1a, or HDMI 1.4b) Integrated Intel HD Graphics (Gen9) GPU; PCI Express 2.0 controller supporting 6 lanes (3 dedicated and 3 multiplexed with USB 3.0); 4 lanes available ...
Low-density parity-check (LDPC) codes are a class of highly efficient linear block codes made from many single parity check (SPC) codes. They can provide performance very close to the channel capacity (the theoretical maximum) using an iterated soft-decision decoding approach, at linear time complexity in terms of their block length.
It records memory errors, using the EDAC tracing events. EDAC is a Linux kernel subsystem that handles detection of ECC errors from memory controllers for most chipsets on i386 and x86_64 architectures. EDAC drivers for other architectures like arm also exists.
[1] [2] One simple scheme to perform this function scatters the bits of a Hamming code ECC word across multiple memory chips, such that the failure of any single memory chip will affect only one ECC bit per word. This allows memory contents to be reconstructed despite the complete failure of one chip.