Search results
Results from the WOW.Com Content Network
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It is a JEDEC standard (JESD79-2); first published in September 2003. [2] DDR2 succeeded the original DDR SDRAM specification, and was itself succeeded by DDR3 SDRAM in 2007.
DDR and DDR2 memory is usually installed in single- or dual-channel configuration. DDR3 memory is installed in single-, dual-, tri-, and quad-channel configurations. Bit rates of multi-channel configurations are the product of the module bit-rate (given below) and the number of channels.
DDR2 was in turn superseded by DDR3 SDRAM, which offered higher performance for increased bus speeds and new features. DDR3 has been superseded by DDR4 SDRAM, which was first produced in 2011 and whose standards were still in flux (2012) with significant architectural changes. DDR's prefetch buffer depth is 2 (bits), while DDR2 uses 4.
Corresponding 240-pin DIMMs are known as PC2-3200 through PC2-6400. DDR2 SDRAM is now available at a clock rate of 533 MHz generally described as DDR2-1066 and the corresponding DIMMs are known as PC2-8500 (also named PC2-8600 depending on the manufacturer). Performance up to DDR2-1250 (PC2-10000) is available.
The naming convention for DDR, DDR2 and DDR3 modules specifies either a maximum speed (e.g., DDR2-800) or a maximum bandwidth (e.g., PC2-6400). The speed rating (800) is not the maximum clock speed, but twice that (because of the doubled data rate). The specified bandwidth (6400) is the maximum megabytes transferred per second using a 64-bit width.
DDR2 DDR3: Callisto 545, 550, 555, 560, 565, 570 2/4 3000–3400 2000 HT 512 6144 DDR2 DDR3: Athlon II: Propus 4 2200–2800 2000 HT 512 DDR2 DDR3: MMX, SSE, SSE2, SSE3, SSE4a, Enhanced 3DNow! Cool'n'Quiet: AMD64, NX bit, AMD-V: Rana 3 2200–3100 2000 HT 512 DDR2 DDR3: Regor 2 1600–3600 2000 HT 512, 1024 DDR2 DDR3: Sempron: Sargas 130 1 2600 ...
What determines absolute latency (and thus system performance) is determined by both the timings and the memory clock frequency. When translating memory timings into actual latency, timings are in units of clock cycles, which for double data rate memory is half the speed of the commonly quoted transfer rate. Without knowing the clock frequency ...
A memory rank is a set of DRAM chips connected to the same chip select, which are therefore accessed simultaneously.In practice all DRAM chips share all of the other command and control signals, and only the chip select pins for each rank are separate (the data pins are shared across ranks).