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An agree predictor is a two-level adaptive predictor with globally shared history buffer and pattern history table, and an additional local saturating counter. The outputs of the local and the global predictors are XORed with each other to give the final prediction.
The local predictor is a two-level table which records the history of individual branches. It consists of a 1,024-entry by 10-bit branch history table. A two-level table was used as the prediction accuracy is similar to that of a larger single-level table while requiring fewer bits of storage. It has a 1,024-entry branch prediction table.
2014 (For MICRO 1991) Two-Level Branch Predictor; 2014 (For MICRO 1982) MIPS: A Microprocessor Architecture; 2014 (For MICRO 1981) Some Scheduling Techniques and An Easily Schedulable Horizontal Architecture for High Performance Scientific Computing; 2014 (For MICRO 1978) Microprogrammed Implementation of A Single Chip Microprocessor
This approach is employed in a variety of areas, including branch prediction in pipelined processors, value prediction for exploiting value locality, prefetching memory and files, and optimistic concurrency control in database systems. [1] [2] [3] Speculative multithreading is a special case of speculative execution.
Elimination of unnecessary branch instructions can make the execution of necessary branches, such as those that make up loops, faster by lessening the load on branch prediction mechanisms. Elimination of the cost of a branch misprediction which can be high on deeply pipelined architectures.
The general rule for a two-level adaptive predictor with an n-bit history is that it can predict any repetitive sequence with any period if all n-bit sub-sequences are different.[8] The advantage of the two-level adaptive predictor is that it can quickly learn to predict an arbitrary repetitive pattern.
Superscalar, branch prediction PowerPC e500: Dual 7 stage Multi-core PowerPC e600: 3-issue 7 stage Superscalar out-of-order execution, branch prediction PowerPC e5500: 2010 4-issue 7 stage Out-of-order, multi-core PowerPC e6500: 2012 Multi-core PowerPC 603: 4 5 execution units, branch prediction, no SMP PowerPC 603q: 1996 5 In-order PowerPC 604 ...
The first machine to use out-of-order execution was the CDC 6600 (1964), designed by James E. Thornton, which uses a scoreboard to avoid conflicts. It permits an instruction to execute if its source operand (read) registers aren't to be written to by any unexecuted earlier instruction (true dependency) and the destination (write) register not be a register used by any unexecuted earlier ...