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FIPS 140-3 testing began on September 22, 2020, and a small number of validation certificates have been issued. FIPS 140-2 testing was available until September 21, 2021, creating an overlapping transition period of one year. FIPS 140-2 test reports that remain in the CMVP queue will still be granted validations after that date, but all FIPS ...
Current list of FIPS 140 validated cryptographic modules with validated AES implementations (hosted by NIST) – Most of these involve a commercial implementation of AES algorithms. Look for "FIPS-approved algorithms" entry in the "Level / Description" column followed by "AES" and then a specific certificate number.
As of October 2020, FIPS 140-2 and FIPS 140-3 are both accepted as current and active. [1] FIPS 140-3 was approved on March 22, 2019 as the successor to FIPS 140-2 and became effective on September 22, 2019. [2] FIPS 140-3 testing began on September 22, 2020, and a small number of validation certificates have been issued.
Due to the critical role they play in securing applications and infrastructure, general purpose HSMs and/or the cryptographic modules are typically certified according to internationally recognized standards such as Common Criteria (e.g. using Protection Profile EN 419 221-5, "Cryptographic Module for Trust Services") or FIPS 140 (currently the 3rd version, often referred to as FIPS 140-3).
This table denotes, if a cryptography library provides the technical requisites for FIPS 140, and the status of their FIPS 140 certification (according to NIST's CMVP search, [27] modules in process list [28] and implementation under test list).
For example, FIPS 140-3, "Security Requirements for Cryptographic Modules," specifies security requirements for cryptographic systems and is widely adopted by both government and private sector organizations requiring robust encryption capabilities.
BitLocker originated as a part of Microsoft's Next-Generation Secure Computing Base architecture in 2004 as a feature tentatively codenamed "Cornerstone" [4] [5] and was designed to protect information on devices, particularly if a device was lost or stolen.
Before the AES-specific instructions were available on RISC-V, a number of RISC-V chips included integrated AES co-processors. Examples include: Dual-core RISC-V 64 bits Sipeed-M1 support AES and SHA256. [26] RISC-V architecture based ESP32-C (as well as Xtensa-based ESP32 [27]), support AES, SHA, RSA, RNG, HMAC, digital signature and XTS 128 ...