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2. List of AMD Ryzen processors - Wikipedia

   en.wikipedia.org/wiki/List_of_AMD_Ryzen_processors

   Common features of Ryzen 7045 notebook CPUs: Socket: FL1. All the CPUs support DDR5-5200 in dual-channel mode. L1 cache: 64 KB (32 KB data + 32 KB instruction) per core. L2 cache: 1 MB per core. All the CPUs support 28 PCIe 5.0 lanes. Native USB 4 (40Gbps) Ports: 0; Native USB 3.2 Gen 2 (10Gbps) Ports: 4

3. List of AMD processors - Wikipedia

   en.wikipedia.org/wiki/List_of_AMD_processors

   Zen 2 series CPUs and APUs (released 2019) Matisse Ryzen 3000 series (desktop) Castle Peak Ryzen Threadripper 3000 series (desktop) Renoir Ryzen 4000 APU series with RX Vega (desktop & laptop) Lucienne Ryzen 5000 APU series (laptop) Mendocino Ryzen 7020 APU series (laptop) and Athlon 7020 APU series (laptop) Rome Epyc 7002 series (server)

4. Table of AMD processors - Wikipedia

   en.wikipedia.org/wiki/Table_of_AMD_processors

   Ryzen 3 (Pro 1200, 1200, Pro 1300, 1300X) 4 No 3100–3500 (3400–3700 boost) 8.0 ... List of AMD CPU microarchitectures; List of AMD mobile microprocessors;

5. Ryzen - Wikipedia

   en.wikipedia.org/wiki/Ryzen

   AMD announced a new series of processors on December 13, 2016, named "Ryzen", and delivered them in Q1 2017, [4] the first of several generations. The 1000 series featured up to eight cores and sixteen threads, with a +52 percent instructions per cycle (IPC) increase over their prior CPU products, namely AMD's previous Excavator microarchitecture.

6. List of AMD mobile processors - Wikipedia

   en.wikipedia.org/wiki/List_of_AMD_mobile_processors

   Common features of Ryzen 5000 notebook APUs: Socket: FP6. All the CPUs support DDR4-3200 or LPDDR4-4266 in dual-channel mode. L1 cache: 64 KB (32 KB data + 32 KB instruction) per core. L2 cache: 512 KB per core. All the CPUs support 16 PCIe 3.0 lanes. Includes integrated GCN 5th generation GPU. Fabrication process: TSMC 7FF.

7. List of AMD chipsets - Wikipedia

   en.wikipedia.org/wiki/List_of_AMD_chipsets

   The UMI interface previously used by AMD for communicating with the FCH is replaced with a PCIe connection. Technically the processor can operate without a chipset; it only continues to be present for interfacing with low speed I/O. AMD server CPUs adopt a self contained system on chip design instead which doesn't require a chipset. [11] [12 ...