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Socket TR4, also known as Socket SP3r2, is a zero insertion force land grid array (LGA) CPU socket designed by AMD supporting its first- and second-generation Zen-based Ryzen Threadripper desktop processors, [1] [2] launched on August 10, 2017 [3] for the high-end desktop and workstation platforms.
AM3+ socket support AMD 990X chipset RD980 2600 (HT 3.0) x8 + x8 x8 + x8 14 Two PCIe 2.0 x16, IOMMU. AM3+ socket support AMD 990FX chipset RD990 x16 + x16 or x8 quad x16 + x16 or x16 + x8 + x8 or x8 quad 19.6 Four PCIe 2.0 x16, IOMMU. AM3+ socket support Model Code name Released CPU support Fab (nm) HT (MHz) AMD-V (Hardware Virtualization) IGP ...
Common features of Ryzen 1000 HEDT CPUs: Socket: TR4. All the CPUs support DDR4-2666 in quad-channel mode. All the CPUs support 64 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset. No integrated graphics. L1 cache: 96 KB (32 KB data + 64 KB instruction) per core. L2 cache: 512 KB per core.
Socket TR4: Quad-channel DDR4: January 2019: Picasso Ryzen 3 (3300U, Pro 3300U, 3350U) ... List of AMD Ryzen microprocessors; List of AMD processors with 3D graphics;
Common features of Ryzen 2000 HEDT CPUs: Socket: TR4. All the CPUs support DDR4-2933 in quad-channel mode. All the CPUs support 64 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset. No integrated graphics. L1 cache: 96 KB (32 KB data + 64 KB instruction) per core. L2 cache: 512 KB per core.
The Ryzen 7000 mobile series initially launched in September 2022 with the Ryzen 7020 Mendocino line of low-end Zen 2 ultra mobile processors. [ 79 ] In early 2023, the rest of the Ryzen 7000 mobile lineup was released, starting with Ryzen 7030, Ryzen 7035, and later Ryzen 7045 and Ryzen 7040 series processors.
Socket sWRX8, also known as Socket SP3r4, is a land grid array (LGA) CPU socket designed by AMD supporting its Ryzen Threadripper Pro 3000 and 5000 series workstation processors, which are based on Zen 2 and Zen 3 platforms, respectively.
Common features of Ryzen 1000 HEDT CPUs: Socket: TR4. All the CPUs support DDR4-2666 in quad-channel mode. All the CPUs support 64 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset. No integrated graphics. L1 cache: 96 KB (32 KB data + 64 KB instruction) per core. L2 cache: 512 KB per core.
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