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For power-of-2 integer division, a simple binary counter can be used, clocked by the input signal. The least-significant output bit alternates at 1/2 the rate of the input clock, the next bit at 1/4 the rate, the third bit at 1/8 the rate, etc. An arrangement of flipflops is a classic method for integer-n division. Such division is frequency ...
decade counter (separate divide-by-2 and divide-by-5 sections) 14 SN74LS90: 74x91 1 8-bit shift register, serial in, serial out, gated input 14 SN74LS91: 74x92 1 divide-by-12 counter (separate divide-by-2 and divide-by-6 sections) 14 SN74LS92: 74x93 1 4-bit binary counter (separate divide-by-2 and divide-by-8 sections); different pinout for ...
When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This "divide by" feature has application in various types of digital counters.
A prescaler is an electronic counting circuit used to reduce a high frequency electrical signal to a lower frequency by integer division.The prescaler takes the basic timer clock frequency (which may be the CPU clock frequency or may be some higher or lower frequency) and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.
In binary arithmetic, division by two can be performed by a bit shift operation that shifts the number one place to the right. This is a form of strength reduction optimization. For example, 1101001 in binary (the decimal number 105), shifted one place to the right, is 110100 (the decimal number 52): the lowest order bit, a 1, is removed.
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The modulus of a counter is the number of states in its count sequence. The maximum possible modulus is determined by the number of flip-flops. For example, a four-bit counter can have a modulus of up to 16 (2^4). Counters are generally classified as either synchronous or asynchronous.