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In USB 3.0, dual-bus architecture is used to allow both USB 2.0 (Full Speed, Low Speed, or High Speed) and USB 3.0 (SuperSpeed) operations to take place simultaneously, thus providing backward compatibility. The structural topology is the same, consisting of a tiered star topology with a root hub at level 0 and hubs at lower levels to provide ...
For example, a USB 2 PCIe host controller card that presents 4 USB "Standard A" connectors typically presents one 4-port EHCI and two 2-port OHCI controllers to system software. When a high-speed USB device is attached to any of the 4 connectors, the device is managed through one of the 4 root hub ports of the EHCI controller.
The throughput of each USB port is determined by the slower speed of either the USB port or the USB device connected to the port. High-speed USB 2.0 hubs contain devices called transaction translators that convert between high-speed USB 2.0 buses and full and low speed buses. There may be one translator per hub or per port.
The idle line state is when the device is connected to the host with a pull-up on either D+ (for full speed USB 1.x) or D− (for low speed USB 1.x), with transmitter output on both host and device is set to high impedance (hi-Z) (disconnected output). A USB device pulls one of the data lines high with a 1.5 kΩ resistor.
USB 3.0 SuperSpeed and USB 2.0 High-Speed versions defined USB 3.0 SuperSpeed – host controller (xHCI) hardware support, no software overhead for out-of-order commands; USB 2.0 High-speed – enables command queuing in USB 2.0 drives; Streams were added to the USB 3.0 SuperSpeed protocol for supporting UAS out-of-order completions
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To allow high-speed (USB 2.0) devices to operate in their fastest mode, all hubs between the devices and the computer must be high-speed. High-speed devices should fall back to full-speed (USB 1.1) when plugged into a full-speed hub (or connected to an older full-speed computer port). While high-speed hubs can communicate at all device speeds ...
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