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The SPARC T4 is a SPARC multicore microprocessor introduced in 2011 by Oracle Corporation. The processor is designed to offer high multithreaded performance (8 threads per core, with 8 cores per chip), as well as high single threaded performance from the same chip. [1] The chip is the 4th generation [2] processor in the T-Series family.
[6] [7] These are branded as the "SPARC T3" series, the "SPARC Enterprise" brand being dropped. The SPARC T3-series servers include the T3-1B, a blade server module that fits into the Sun Blade 6000 system. All other T3 based servers are rack mounted systems. Subsequent T-series server generations also include a blade server in the same Sun ...
The processor uses the same SPARC S3 core design as its predecessor, the SPARC T4 processor, but is implemented in a 28 nm process and runs at 3.6 GHz. [5] The S3 core is a dual-issue core that uses dynamic threading and out-of-order execution, [6] incorporates one floating point unit, one dedicated cryptographic unit per core. [7]
The Oracle Corporation SPARC T3 has eight fine-grained threads per core; SPARC T4, SPARC T5, SPARC M5, M6 and M7 have eight fine-grained threads per core of which two can be executed simultaneously. Fujitsu SPARC64 VI has coarse-grained Vertical Multithreading (VMT) SPARC VII and newer have 2-way SMT.
Oracle SPARC T4: 2011 16 Multithreading, multi-core, 8 fine-grained threads per core of which 2 can be executed simultaneously, 2-way simultaneous multithreading, SMP, 8 cores per chip, out-of-order, 4 MB L3 cache, out-of order, Hardware random number generator Oracle Corporation SPARC T5: 2013 16
There are a maximum of two root domains for the UltraSPARC T1 (Niagara) servers, one of which also must be the control domain. UltraSPARC T2 Plus, SPARC T3, and SPARC T4 servers can have as many as 4 root domains, limited by the number of PCIe root complexes installed on the server. SPARC T5 servers can have up to 16 root complex domains.
SPARC version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended-precision" floating-point arithmetic to 128-bit " quad-precision " arithmetic.
Pages in category "SPARC microprocessors" ... SPARC M7; SPARC M8; SPARC T3; SPARC T4; SPARC T5; HAL SPARC64; SPARC64 GP; SPARC64 I; SPARC64 II; SPARC64 III; SPARC64 IXfx;