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Intel Celeron Mendocino 300 MHz in SEPP package Top of a Mendocino-core Socket 370 Celeron (PPGA package) Underside of a Mendocino-core Socket 370 Celeron, 333 MHz Intel Celeron 500MHz Mendocino die shot. The Mendocino Celeron, launched August 24, 1998, was the first retail CPU to use on-die L2 cache. Whereas Covington had no secondary cache at ...
Intel initially listed the Celeron 900 as Dual-Core and with Virtualization Technology in its Processorfinder and ARK databases, which caused confusion among customers. ULV 723 possibly supports EIST, but Intel's web site is inconsistent about this.
Socket 370 started out as a budget-oriented platform for 66 MHz FSB PPGA Mendocino Celeron CPUs in late 1998, as the move to on-die L2 cache eliminated the need for a PCB design as seen on Slot 1. Socket 370 then became Intel's main desktop socket from late 1999 to late 2000 for 100/133 MHz FSB FC-PGA Coppermine Pentium IIIs.
A common overclock involved the pin-40 hack, or using an ABIT BP6 or Asus P2B, and setting the bus speed on a 66 MHz Covington or Mendocino-core Celeron to 100 MHz. The Mendocino-core Celeron 300A became a "sweet spot" for overclockers, with nearly 100% success rates at reaching 450 MHz on a 100 MHz FSB, allowing it to equate to a much more ...
Socket 370 was initially made for low-cost Celeron processors starting with the Mendocino Celerons, while Slot 1 was thought of as a platform for the more expensive Pentium II and early Pentium III models. Both cache and core were embedded into the die.
2.14.5 Celeron M (64-bit Core microarchitecture) 2.15 64-bit processors: Intel 64 – Nehalem microarchitecture. ... Mendocino – 0.25 μm process technology.
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The Deschutes core Pentium II (80523), which debuted at 333 MHz in January 1998, was produced with a 0.25 μm process and has a significantly lower power draw. [15] The die size is 113 mm 2 . The 333 MHz variant was the final Pentium II CPU that used the older 66 MT/s front-side bus ; all subsequent Deschutes-core models used a 100 MT/s FSB.